Two-dimensional imaging is undeniably useful for finding faults in integrated circuits. For peering into the intricate depths of multilevel ICs, however, 3-D methods are required. A group of researchers recently imaged an IC interconnecta premier example of a 3-D structureat a resolution of 400 nm  using scanned X-ray nanotomography. Led by researcher Zachary Levine at the National Institute of Standards and Technology (NIST; Gaithersburg, MD; 301-975-5453), the team included scientists from Rensselaer Polytechnic Institute (RPI; Troy, NY), the DOE's Argonne National Laboratory (Argonne, IL), and Digital Equipment Corp. (Hudson, MA).
In their work, the researchers used scanned X-ray nanotomography to obtain 3-D images from an aluminum-tungsten interconnect (see Figure below). The sample was scanned across a 200-nm focal spot of 1573 eV radiation from Argonne's Advanced Photon Source synchrotron. While synchrotron radiation is necessary at this point, laser plasma sources might eventually be usable, turning the method into a viable industrial tool for early production or failure analysis.
The researchers imaged a three-level IC in which two levels of aluminum wires are connected by tungsten vias inside the silica, and several focused ion beam markers are embedded in the surface. A 250-micron diameter region of the standard silicon 3-mm wafer was thinned to about 10 microns. Once the sample was in the beam, X-rays passing through the sample were detected with an avalanche photodiode. A raster scan of the sample used 301 x 301 pixels in nominally 50-nm steps. Thirteen images were obtained, each at a slightly different angle to the beam, then aligned to create a 3-D reconstruction.
Tomographic image of an integrated circuit. The isolated blobs are focused ion beam markers. Metal wires are visible to the left. The vias are seen as short protruding segments.
Transmission electron microscopes (TEMs) can provide 3-D images of integrated circuits, but their high resolution (smaller than a nanometer) and small fields of view make them too fine a tool for applications such as multilayer interconnects. TEM samples are typically thinned to 200 nm, although high-voltage TEMs can image through a micron or two. In contrast, multilayer interconnects tend to be 5- to 15-microns thick. This is far too deep for TEM, but scanned X-ray tomography can image through this depth.
A larger-resolution, larger field-of-view method is also needed to image flaws in logic circuits. Because logic circuits are irregular, the flaws cannot be localized as easily as in memory circuits, and thus the desired field of view is larger.
"X-ray tomography has the potential to be a useful research tool for ICs, particularly for fault analysis," says Waleed Haddad of the DOE's Lawrence Livermore National Laboratory. "But for it to be a manufacturing tool, really major advances, at least in light sources," must occur. Levine explains: laser plasma sources are lab-sized devices that generate X-rays, but they emit in all directions, unlike the focused beam produced by a synchrotron. If the optics for these laser plasma sources could gather and focus the radiation, then they might be a feasible source.
Levine says, "If you could get within a factor of five of the theoretical limit of a Wolter optic, then you could get off the [synchrotron] ring." Then chip-makers could afford in-house instruments. "It comes down to speed and the cost to acquire data," Haddad says. Depending on a synchrotron severely limits sample throughput.
For now, the researchers are focused on improving the resolution of their system. The next run will attempt to deliver 150-nm resolution. Because quarter-micron feature devices are already in production, the resolution will have to be even smaller than that to show the shapes of the wires. Eventually, Levine says, "we want 50-nm resolution."
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Yvonne Carts-Powell is a freelance writer based in Massachusetts.