Identifying Semiconductor Wafer Defects With Emission Microscopes

By Tom Adams

Emission microscopes intensify the light emitted by chip-level defects and produce an image showing the defect location on the chip. Both static (leakage) and functional (dynamic) defects are located in this way. After a defect has been located, further SEM or FIB analysis identifies the nature and cause of the defect. Defects can also be located by manual probing, but the man-hours required are proportional to the complexity and density of the chip. Manual probing of one of today's advanced chip designs can take a month or more. This is why the emission microscope - a useful novelty when it was introduced by Hypervision in 1986 - has become a necessity.

Until recently all emission microscope work was performed from the front side of a device or wafer. Even if the defect was located under metallization, the light emitted would escape from the front of the chip. Often the light was reflected several times between the metallization and the silicon before escaping, but the intensity was still more than adequate.

In the early 90s new chip designs made it impossible for light to escape from the front. Chips with 3 or more layers of metallization don't allow enough light to escape, while in Lead-on-Chips the light escapes to the front but is blocked because the probe needles must reach the pads in the middle of the chip to deliver the signals for testing. Designs where frontside emission imaging is impossible will proliferate because, as design rules shrink, the number of layers of metallization will increase.

Fortunately, defects emit light in all directions - including toward the backside of the chip. Silicon, partly transparent to the wavelengths emitted by the defects, acts as a filter. The more doping in the silicon, the more restrictive the filter. Early experiments showed that the light from defects could be gathered at the backside, but that the backside silicon would have to be thinned to reduce the filter effect. Adequate thinning, however, made light emissions as accessible from the backside as they had been from the frontside.

After much experimentation, Hypervision developed an instrument which successfully thins backside silicon on devices in 1996. The tool had to overcome two major problems: silicon is both brittle and very hard, and great precision is needed in all 3 axes. The automated instrument uses a coolant spray to keep temperature low and a diamond-coated end mill which is computer numerically controlled. It opens a square or rectangular window in the backside silicon of the device, and leaves a "floor" of remaining silicon which may be as thin as 50 microns. In the final step, the floor is polished to enhance illumination through the silicon. The final emission image is an overlay of the emission site itself and an illuminated image showing circuitry and permitting x,y location of the defect.

Wafers are far more fragile than devices, and finding techniques for successfully thinning and then probing individual devices on wafers required further research. The entire wafer cannot be thinned: if a 6-inch wafer is thinned to 50 microns, the result is a brittle structure whose width is 3,000 times greater than its thickness.

Any attempt to perform emission microscope imaging on wafers involves two separate problems: 1) the backside silicon over individual target chips must be thinned safely; and 2) after thinning, the target chip must be probed from the front side.

Research into the load-bearing and fracture characteristics of wafers showed that square or rectangular windows could not be used to observe the backside of wafers. The straight-line edges of these cutouts cause cracks to propagate across the wafer. Instead, circular cutouts are used. Wafer milling is, however, otherwise similar to the removal of backside silicon from devices.

The floor of the circular cutout is still very fragile. Cementing an optical-glass insert slightly less than the diameter of the cutout to the floor cubes its stiffness. The insert also enhances the illuminated image.

Existing probe needles and cards generated too much force against the front of the chip to be borne by the silicon remaining in the circular cutout, even when reinforced by the insert. New high-conductivity, ultra low force probe needles give the same performance but reduce the force against the circuitry to less than 10% of the force of conventional probe needles.

The steps in the backside thinning and emission imaging of a wafer are described below.

1. To protect the face of the wafer during backside milling, a sheet of flexible Gel-Pak is applied. A low-tack adhesive permits later removal without damage to frontside circuitry.

2. A second Gel-Pak sheet, with a circular cutout over the backside of the target chip, is applied to the back of the wafer.

3. The two sheets are sealed around the edge of the wafer. Except for the cutout on the backside over the target chip, the entire wafer is now encapsulated.

4. Food-grade paraffin wax is used to mount the encapsulated wafer on a solid chuck.

5. Backside milling is performed to reduce the backside silicon. The spray coolant keeps the temperature at the mill head below 200° C. (Dry milling would produce temperatures of 600-700° C., and would anneal or melt aluminum traces.) The coolant also reduces the hardness of the surface of the silicon by about 60%. The cutout in the backside Gel-Pak acts as a dam for the coolant.

6. Automated milling continues until the desired thickness of remaining silicon - typically from 50 microns to 200 microns - is reached.

7. The floor of the cutout is automatically polished.

8. The optical glass insert is cemented into the cutout.

9. Low heat is applied to melt the paraffin wax and remove the encapsulated wafer from the chuck.

10. The Gel-Pak sheets are removed from the wafer.

11. The wafer is mounted face-down on a chuck for emission imaging. This chuck holds the wafer only by the edges. Newer alternate backside chuck designs have holes which support all of the wafer except the cut-out.

12. The ultra low force probe needles are applied to the face of the chip. The chip is biased. If functional (dynamic) defects are being investigated, test vectors are introduced from ATE equipment.

Ultra low force probe card developed by Hypervision.

13. Light emitted by defects escapes to the back of the wafer through the thinned silicon and is captured and intensified by the emission microscope.

14. Backside illumination is used to illuminate the chip's circuitry through the remaining silicon. The optical insert enhances the quality of this image.

15. The emission image and the optical image are overlaid to produce the final emission image showing the location of the defect. Various additional steps may be taken here, such as the use of subtraction software to remove light from natural emitters.

Backside emission image through thinned wafer.

Same backside image as above, but inverted by software to give "normal" frontside perspective.

Backside image through thinned wafer showing defects (red).

About the author
Tom Adams is a writer and photomicrographer who has written widely on semiconductor subjects. He is based in Lawrenceville, NJ.