Executive Perspective: Interview with Michael Thomas, chief technical officer, Honeywell Electronic Materials

Laboratory Network: From your perspective, what are some of the emerging trends in the electronic materials marketplace?

We see a continual movement toward higher performance, lower processing costs and process extendability. Take performance. A little more than two years ago you had Pentium and K6 microprocessors running at 266 MHz as the standard. Now you see the advent of higher performance microprocessors running at frequencies of over 1 GHz. The employment of low-k dielectric materials in multilevel interconnect architectures of future devices will allow even greater performance at lower power consumption and manufacturing costs. These changes are expected to occur at the 130 nm node, where low-k dielctrics will be coupled with copper wiring.

LN: What is Honeywell doing to address the need for low-k dielectrics?

We're focusing on "interconnect solution" strategies. This means we're utilizing our core competencies in materials science and polymer chemistry to synthesize a wide range of low-k dielectric materials. These materials will meet the high temperature and mechanical requirements associated with advanced interconnect processing. In addition, we are generating novel stacked dielectric systems which have substantially lower effective k's than competitive offerings.

Since we also have a strong metallurgical bench strength, we provide the key metals associated with interconnect processing solutions and can address all aspects of the interconnect equation that merge low-k materials and metals. Additionally, we provide other materials that aid in the thermal management and array bonding of advanced VLSI circuits.

It is our intention to provide material and process solutions from the contact level through packaging operations in support of our "layer one to package done" philosophy. By bringing our portfolio of new materials to bear on the interconnect problem, we're providing flexible "enabling technologies" for the next generation of semiconductor devices.

LN: What do you mean by "enabling" technologies?

I mean a number of things. One is that we can enable improved cost performance. We also enable a simple low-k integration methodology, where manufacturers can employ the same tool set over many device generations. By providing a low-k process, which uses only spin-on deposition tooling, we can provide a straightforward path to effective dielectric constants (k<2), which were not considered achievable over the next five years of IC manufacturing. So by engineering our materials properly and showing our customers how to use them in an interconnect application, we can enable our customers with processes not available using other technologies.

LN: Honeywell already has a strong position in semiconductor chemicals, doesn't it?

Oh yes. To give you an idea, there's something like 40 million 8-inch wafers fabricated per year in the world. If you look at the fabrication of these wafers, from a materials science and chemistry point of view, we've made a substantial contribution to the industry. I would say at least 50% of the memories you have in your computer have some form of our dielectric material in them, and probably 60% to 70% of the chips use metallizations generated from our sputtering targets.

LN: That dielectric technology came from AlliedSignal, didn't it?

Yes. AlliedSignal [now Honeywell] has been working in dielectric spin-on materials for the semiconductor industry for 10 to 15 years. Last year they also acquired Johnson Matthey [a leader in production of sputtering and packaging-related metallurgies for the semiconductor industry]. This was a very critical acquisition for us because it brought together the two major core components that technologists use in the fabrication of on-chip interconnects – dielectrics and metals. The combination of these two technologies under one technical umbrella has uniquely positioned Honeywell Electronic Materials with a materials bench strength unmatched by any supplier in the semiconductor industry.

LN: What are some of the features of Honeywell's latest spin-on dielectric polymers?

We have two families of them that provide flexibility to our customers. One is wholly organic, which we call FLARE. The other family is based on siloxane backbone polymers that involve two key materials called HOSP and Nanoglass. They both can take processing temperatures up to 450º C. You can use either one or you can mix them, depending on your needs. Actually, they provide processing simplicity when used together.

LN: How are the spin-on dielectrics superior in performance to dielectrics applied by the competing CVD process?

As I said, the dielectric has to have a low k [permittivity] value for high performance. From data reported to the industry, we don't believe CVD films can deliver an "effective k" value lower than about 2.8, whereas our materials have the potential to achieve effective k's at or below 2.0. Although individual CVD films can approach k values around 2.5, when they are integrated with other materials, like CVD nitrides or carbides for stop layers, the effective dielectric constant is negatively impacted. Spin-on dielectrics can be designed to avoid these penalties and provide unique advantages in processing and performance. To date, two major manufacturers have validated our materials in multilevel copper DD applications.

LN: You mentioned lower processing costs as another trend in the semiconductor industry. What advantages do your spin-on dielectric polymers have in this regard?

If you look at the semiconductor industry today, maybe 80% of the cost of a factory is in tools. So manufacturers have to be extremely careful about getting good utility out of their tool sets over three or four device generations. At present, CVD technologies are very equipment-intensive, where tools are more complex and costly when compared to spin coating equipment.

We have shown on a number of spin tools that spin-on materials are already mature for 300 mm processing. We believe that by modifying only the materials, the spin-on approach allows tools bought for 130 nm generations and beyond to not require major enhancements, while also offering reduced manufacturing risks. So manufacturers can extend the low-k dielectric technology for several device generations by designing the changing science into their materials without having to change their tool set. This means they don't have to buy new or more complicated tools during this time. In fact, once they've depreciated their tool set, their price per wafer goes substantially down.

LN: You mean that users of CVD systems will have to retool with each device generation?

We think that the probability of retooling is much higher for CVD compared to spin coating processes. Since lower k CVD process options are in the exploration phase, with no guarantee of a solution, there is a high chance that new tooling may be required. Presently, data that has been generated by IBM and SONY indicates they haven't seen any material options in CVD that can match spin-on effective k values that need to be employed in production.

LN: Are you offering any products in connection with the newly emerging copper interconnects?

Yes. As I mentioned earlier, Honeywell Electronic Materials has for some time been making high-purity PVD tantalum and copper targets needed for the barrier/seed metallizations used in dual-damascene interconnect structures. These metallizations are key to the successful filling of damascene features using copper Electrochemical Deposition (ECD).. We're working on all the metallurgies that will continue to support copper interconnect at progressively smaller feature sizes and merging these technologies with spin-on, low-k dielectric materials. So it's copper and low-k. Both are needed to enhance performance, reduce power consumption and lower costs.